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Publications and Achievements

Last modified by Satoshi Ohtake on 2018/09/30 23:58

Book Chapter

  1. VLSI-SoC: Research Trends in VLSI and Systems on Chip (Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "Broadside transition test generation for partial scan circuits through stuck-at test generation," pp.301-316), Edited by Giovanni De Micheli, Salvador Mir, and Ricardo Reis, Springer, 2008.

Journal Papers

  1. Hideo Fujiwara, Satoshi Ohtake and Tomoya Takasaki, "Sequential circuit structure with combinational test generation complexity and its application," Trans. of IEICE(D-I), Vol. J80-D-I, No. 2, pp.155-163, Feb. 1997. (In Japanese)
    (IEICE ISS 2001 Year Paper Award received, Sep. 2002)
  2. Satoshi Ohtake, Tomoo Inoue and Hideo Fujiwara, "An approach to sequential test generation by circuit pseudo-transformation," IPSJ Journal, Vol. 38, No. 5, pp.1040-1049, May 1997. (In Japanese)
  3. Satoshi Ohtake, Toshimitsu Masuzawa and Hideo Fujiwara, "A non-scan DFT method for controllers to provide complete fault efficiency," Trans. of IEICE (D-I), Vol. J81-D-I, No. 12, pp.1259-1270, Dec. 1998. (In Japanese)
     (IEICE ISS 2001 Year Paper Award received, Sep. 2002)
  4. Satoshi Ohtake, Toshimitsu Masuzawa and Hideo Fujiwara, "A non-scan approach to DFT for controllers achieving 100% fault efficiency," Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 16, No. 5, pp.553-566, Oct. 2000.
  5. Shintaro Nagai, Hiroki Wada, Satoshi Ohtake and Hideo Fujiwara, "A non-scan DFT method for RTL circuits based on fixed-control testability," Trans. of IEICE (D-I), Vol. J84-D-I, No. 5, pp.454-465, May 2001. (In Japanese)
     (IEICE ISS 2001 Year Paper Award received, Sep. 2002)
  6. Shintaro Nagai, Satoshi Ohtake and Hideo Fujiwara, "A method of design for hierarchical testability for data flow intensive circuits at register-transfer level," IPSJ Journal, Vol. 43, No. 5, pp.1278-1289, May 2002. (In Japanese)
  7. Md. Altaf-Ul-Amin, Satoshi Ohtake and Hideo Fujiwara, "Design for hierarchical two-pattern testability of data paths," IEICE Trans. on Information and Systems, Vol. E85-D, No. 6, pp.975-984, June 2002.
  8. Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa and Hideo Fujiwara, "A non-scan DFT method at register-transfer level to achieve 100% fault efficiency," IPSJ Journal, Vol. 44, No. 5, pp.1266-1275, May 2003.
  9. Md. Altaf-Ul-Amin, Satoshi Ohtake and Hideo Fujiwara, "Design for two-pattern testability of controller-data path circuits," IEICE Trans. on Information and Systems, Vol. E86-D, No. 6, pp.1042-1050, June 2003.
  10. Shunjiro Miwa, Satoshi Ohtake and Hideo Fujiwara, "A new class of sequential circuits with combinational test generation complexity for path delay faults," Trans. of IEICE(D-I), Vol. J86-D-I, No. 11, pp.809-820, Nov. 2003. (In Japanese)
  11. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "A test generation method for path delay faults in sequential circuits with discontinuous reconvergence structure," Trans. of IEICE (D-I), Vol. J86-D-I, No. 12, pp.872-883, Dec. 2003. (In Japanese)
  12. Debesh K. Das, Satoshi Ohtake and Hideo Fujiwara, "New non-scan DFT techniques to achieve 100% fault efficiency," Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 20, No. 3, pp.315-323, June 2004.
  13. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "A design scheme for delay testing of controllers using state transition information," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E87-A, No. 12, pp.3200-3207, Dec. 2004.
  14. Kouhei Ohtani, Satoshi Ohtake and Hideo Fujiwara, "A test generation method for path delay faults using stuck-at fault test generation algorithms," Trans. of IEICE (D-I), Vol. J88-D-I, No. 6, pp.1057-1064, June 2005. (In Japanese)
  15. Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara, "Non-scan design for single-port-change delay fault testability," IPSJ Journal, Vol. 47, No. 6, pp.1619-1628, June 2006.
  16. Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake and Hideo Fujiwara, " A DFT method based on partially strong testability of RTL data paths to guarantee complete fault efficiency," Trans. of IEICE (D), Vol. J89-D, No. 8, pp.1643-1653, Aug. 2006. (In Japanese)
  17. Masato Nakazato, Satoshi Ohtake, Kewal K. Saluja and Hideo Fujiwara, "Acceleration of test generation for sequential circuits using knowledge obtained from synthesis for testability," IEICE Trans. on Information and Systems, Vol. E90-D, No. 1, pp.296-305, Jan. 2007.
  18. Masato Nakazato, Michiko Inoue, Satoshi Ohtake and Hideo Fujiwara, "Design for testability method to avoid error masking of software-based self-test for processors," IEICE Trans. on Information and Systems, Vol. E91-D, No. 3, pp.763-770, Mar. 2008.
  19. Hiroshi Iwata, Satoshi Ohtake and Hideo Fujiwara, "A method of path mapping from RTL to gate level and its application to false path identification," IEICE Trans. on Information and Systems, Vol.E93-D, No.7, pp.1857-1865, July 2010.
  20. Marie Engelene Jimenez Obien, Satoshi Ohtake, Hideo Fujiwara, "F-scan: A DFT method for functional scan at RTL," IEICE Trans. on Information and Systems, Vol. E94-D, No. 1, pp.104-113, Jan. 2011.
  21. Seiji Kajihara, Satoshi Ohtake,"Logging and Using Field Test Data for Improved Dependability," The Journal of Reliability Engineering Association of Japan, Vol. 35, No. 8, pp.513, Dec. 2013. (In Japanese)

Invited Journal Paper

  1. Seiji Kajihara, Satoshi Ohtake and Tomokazu Yoneda, "Delay testing: Improving test quality and avoiding over-testing," IPSJ Transactions on System LSI Design Methodology, Vol.4, No.0, pp.117-130, Aug. 2011.

International Conferences

  1. Satoshi Ohtake, Tomoo Inoue and Hideo Fujiwara, "Sequential test generation based on circuit pseudo-transformation," 6th IEEE Asian Test Symposium (ATS '97), pp.62-67, Nov. 1997.
  2. Satoshi Ohtake, Toshimitsu Masuzawa and Hideo Fujiwara, "A non-scan DFT method for controllers to achieve complete fault efficiency," 7th IEEE Asian Test Symposium (ATS '98), pp.204-211, Dec. 1998.
  3. Debesh K. Das, Satoshi Ohtake and Hideo Fujiwara, "New DFT techniques of non-scan sequential circuits with complete fault efficiency," 8th IEEE Asian Test Symposium (ATS '99), pp.263-268, Nov. 1999.
  4. Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara, "A method of test generation for weakly testable data paths using test knowledge extracted from RTL description," 8th IEEE Asian Test Symposium (ATS '99), pp.5-12, Nov. 1999.
  5. Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa and Hideo Fujiwara, "A non-scan DFT method at register-transfer level to achieve complete fault efficiency," Asia and South Pacific Design Automation Conference 2000 (ASP-DAC 2000), pp.599-604, Jan. 2000.
  6. Satoshi Ohtake, Shintaro Nagai, Hiroki Wada and Hideo Fujiwara, "A DFT method at RTL based on fixed-control testability to achieve 100% fault efficiency," 1st IEEE Workshop on RTL ATPG & DFT (WRTLT '00), Sep. 2000.
  7. Satoshi Ohtake, Shintaro Nagai, Hiroki Wada and Hideo Fujiwara, "A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability," Asia and South Pacific Design Automation Conference 2001 (ASP-DAC 2001), pp.331-334, Jan. 2001.
  8. Debesh K. Das, Bhargab B. Bhattacharya, Satoshi Ohtake and Hideo Fujiwara, "Testable design of sequential circuits with improved fault efficiency," International Conference on VLSI Design 2001, pp.128-133, Jan. 2001.
  9. Md. Altaf-Ul-Amin, Satoshi Ohtake and Hideo Fujiwara, "Design for hierarchical two-pattern testability of data paths," 10th IEEE Asian Test Symposium (ATS '01), pp.11-16, Nov. 2001.
  10. Shintaro Nagai, Satoshi Ohtake and Hideo Fujiwara, "A design for hierarchical testability for RTL data paths using extended data flow graphs," 2nd IEEE Workshop on RTL ATPG and DFT (WRTLT '01), pp.128-133, Nov. 2001.
  11. Satoshi Ohtake, Shunjiro Miwa and Hideo Fujiwara, "A method of test generation for path delay faults in balanced sequential circuits," IEEE VLSI Test Symposium (VTS '02), pp.321-327, May 2002.
  12. Md. Altaf-Ul-Amin, Satoshi Ohtake and Hideo Fujiwara, "Design for two-pattern testability of controller-data path circuits," 11th IEEE Asian Test Symposium (ATS '02), pp.73-79, Nov. 2002.
  13. Satoshi Ohtake, Kouhei Ohtani and Hideo Fujiwara, "A method of test generation for path delay faults using stuck-at fault test generation algorithms," Design Automation and Test in Europe 2003 (DATE '03), pp.310-315, Mar. 2003.
  14. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "A path delay test generation method for sequential circuits based on reducibility to combinational test generation," Digest of Papers of 8th IEEE European Test Workshop (ETW '03), pp.307-312, May 2003.
  15. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "An approach to non-scan design for delay fault testability of controllers," 4th IEEE Workshop on RTL and High Level Testing (WRTLT '03), pp.79-85, Nov. 2003.
    (WRTLT '03 Best Paper Award received)
  16. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "Reducibility of sequential test generation to combinational test generation for several delay fault models," 12th IEEE Asian Test Symposium (ATS '03), pp.58-63, Nov. 2003.
  17. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "A design methodology to realize delay testable controllers using state transition information," Proceedings of 9th IEEE European Test Symposium (ETS '04), pp.168-173, May 2004.
  18. Michel Renovell, Mariane Comte, Satoshi Ohtake and Hideo Fujiwara, "Electrical analysis of a domino logic cell with GOS faults," IEEE International Workshop on Current & Defect Based Testing, pp.34-41, May 2005.
  19. Mariane Comte, Satoshi Ohtake, Hideo Fujiwara and Michel Renovell, "Electrical behavior of GOS faults in domino logic," 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp.210-215, Apr. 2005.
  20. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation," Proceedings of 10th IEEE European Test Symposium (ETS '05), pp.48-53, May 2005.
  21. Masato Nakazato, Satoshi Ohtake and Hideo Fujiwara, "Acceleration of test generation for sequential circuits using knowledge obtained from synthesis for testability," 6th IEEE Workshop on RTL and High Level Testing (WRTLT '05), pp.50-60, July 2005.
     (WRTLT '05 Best Paper Award received)
  22. Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake and Hideo Fujiwara, "A DFT method for RTL data paths based on partially strong testability to guarantee complete fault efficiency," 14th IEEE Asian Test Symposium (ATS '05), pp.306-311, Dec. 2005.
  23. Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara, "Design for testability based on single-port-change delay testing for data paths," 14th IEEE Asian Test Symposium (ATS '05), pp.254-259, Dec. 2005.
  24. Mariane Comte, Satoshi Ohtake, Hideo Fujiwara and Michel Renovell, "Electrical behavior of GOS fault affected domino logic cell," 3rd IEEE International Workshop on Electronic Design, Test & Applications (DELTA 2006), pp.183-189, Jan. 2006.
    (DELTA 2006 Best Paper Award received)
  25. Ilia Polian, Bernd Becker, Masato Nakazato, Satoshi Ohtake and Hideo Fujiwara, "Period of grace: a new paradigm for efficient soft error hardening," 18. ITG/GI/GMM Workshop Testmethoden und Zuverlassigkeit von Schaltungen und Systemen (in Germany), pp.41-45, Mar. 2006.
  26. Yuki Yoshikawa, Satoshi Ohtake and Hideo Fujiwara, "An approach to reduce over-testing of path delay faults in data paths using RT-level information," Digest of Papers of 11th IEEE European Test Symposium (ETS '06), pp.146-151, May 2006.
  27. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "A new test generation model for broadside transition testing of partial scan circuits," IFIP International Conference on Very Large Scale Integration (VLSI-SoC 2006), pp.308-313, Oct. 2006.
  28. Ilia Polian, Bernd Becker, Masato Nakazato, Satoshi Ohtake and Hideo Fujiwara, "Low-cost hardening of image processing applications against soft errors systems," 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI (DFT '06), pp.274-279, Oct. 2006.
  29. Masato Nakazato, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara, "Design for testability of software-based self-test for processors," 15th IEEE Asian Test Symposium (ATS '06), pp.375-380, Nov. 2006.
  30. Satoshi Ohtake, Kosuke Yabuki and Hideo Fujiwara, "Delay testing for application-specific interconnects of FPGAs based on inphase structure," Digest of papers of 12th IEEE European Test Symposium (ETS '07), pp.131-136, May 2007.
  31. Yuki Yoshikawa, Satoshi Ohtake and Hideo Fujiwara, "RTL don't care path identification and synthesis for transforming don't care paths into false paths," 8th IEEE Workshop on RTL and High Level Testing (WRTLT '07), pp.9-15, Oct. 2007.
    (WRTLT'07 Best Paper Award received)
  32. Yuki Yoshikawa, Satoshi Ohtake and Hideo Fujiwara, "False path identification using RTL information and its application to over-testing reduction for delay faults," 16th IEEE Asian Test Symposium (ATS '07), pp.65-68, Oct. 2007.
  33. Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko and Hideo Fujiwara, "Efficient path delay test generation based on stuck-at test generation using checker circuitry," IEEE/ACM International Conference on Computer-Aided Design (ICCAD '07), pp.418-423, Nov. 2007.
  34. Tsuyoshi Iwagaki and Satoshi Ohtake, "Generation of power-constrained scan tests and its difficulty," IEEE International Design and Test Workshop (IDT '07), pp.71-76, Dec. 2007.
  35. Satoshi Ohtake and Kewal K. Saluja, "A systematic scan insertion technique for asynchronous on-chip interconnects," 1st International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR), May 2008.
  36. Hiroshi Iwata, Satoshi Ohtake and Hideo Fujiwara, "An approach to RTL-GL path mapping based on functional equivalence," 9th IEEE Workshop on RTL and High Level Testing (WRTLT'08), pp.63-68, Nov. 2008.
  37. Thomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake and Hideo Fujiwara, "Identifying non-robust untestable RTL paths in circuits with multi-cycle paths," 17th IEEE Asian Test Symposium (ATS'08), pp.125-130, Nov. 2008.
  38. Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue and Hideo Fujiwara, "Fast false path identification based on functional unsensitizability," Asia and South Pacific Design Automation Conference (ASP-DAC 2009), pp.660-665, Jan. 2009.
  39. Satoshi Ohtake, Naotsugu Ikeda, Michiko Inoue and Hideo Fujiwara, "Unsensitizable path identification at RTL using high-level synthesis information," 16th IEEE International Test Synthesis Workshop (ITSW 2009), Mar. 2009.
  40. Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue and Hideo Fujiwara, "A synthesis method to alleviate over-testing of delay faults based on RTL don't care path identification," IEEE VLSI Test Symposium (VTS '09), pp.71-76, May 2009.
  41. Yasuo Sato, Seiji Kajihara, Yukiya Mimura, Tomokazu Yoneda, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara, "A circuit failure prediction mechanism (DART) for high field reliability," 8th IEEE International Conference on ASIC (ASICON2009), pp.581-584, Oct. 2009.
  42. Michiko Inoue, Satoshi Ohtake, Yuichi Uemoto and Hideo Fujiwara, "Path-based resource binding to reduce delay fault test cost," 10th IEEE Workshop on RTL and High Level Testing (WRTLT'09), pp.29-32, Nov. 2009.
  43. Hiroshi Iwata, Satoshi Ohtake and Hideo Fujiwara, "Enabling false path identification from RTL for reducing design and test futileness," in Proceedings of 5th IEEE International Symposium on Electronic Design, Test & Applications (DELTA '10), pp.20-25, Jan. 2010.
  44. Satoshi Ohtake, Naotsugu Ikeda, Michiko Inoue and Hideo Fujiwara, "A method of unsensitizable path identification using high level design information," in Proceedings of 5th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS '10), IEEE Xplore, Mar. 2010.
  45. Satoshi Ohtake, Hiroshi Iwata and Hideo Fujiwara, "A synthesis method to propagate false path information from RTL to gate level" in Proceedings of 13th IEEE International Symposium on Design and Diagnostics of Electronic (DDECS '10), pp.197-200, Apr. 2010.
  46. Marie Engelene Jimenez Obien, Satoshi Ohtake, Hideo Fujiwara, "Delay fault ATPG for F-scannable RTL circuits," in Proceedings of IEEE International Symposium on Communications and Information Technologies (ISCIT'10), IEEE Xplore, Oct. 2010.
  47. Marie Engelene Jimenez Obien, Satoshi Ohtake and Hideo Fujiwara, "Constrained ATPG for functional RTL circuits using F-scan," in Proceedings of IEEE International Test Conference (ITC'10), Paper 21.1, Oct. 2010.
  48. Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara, "Bipartite full scan design: A DFT method for asynchronous circuits," in Proceedings of IEEE Asian Test Symposium (ATS'10), pp.206-211, Dec. 2010.
  49. Marie Engelene Jimenez Obien, Satoshi Ohtake and Hideo Fujiwara, "F-scan test generation model for delay fault testing at RTL using standard full scan ATPG," in Proceedings of IEEE European Test Symposium, p.203, May 2011.
  50. Kazumi Hatayama, Yasuo Sato, Michiko Inoue, Tomokazu Yoneda, Yuta Yamato, Seiji Kajihara, Yukiya Miura and Satoshi Ohtake, "Functional safety enhancement using DART technology for dependable VLSIs," IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012), June 2012.
  51. Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satoshi Ohtake, Takumi Hasegawa, Motoyuki Sato and Kotaro Shimamura, "DART: dependable VLSI test architecture and its implementation," in Proceedings of IEEE International Test Conference, Nov. 2012.
  52. Satoshi Ohtake, Seiji Kajihara, Yasuo Sato, Michiko Inoue, Kazumi Hatayama, Tomokazu Yoneda, Yuta Yamato and Yukiya Miura, "On-chip delay measurement with field test architecture DART," IEEE/ACM Workshop on Variability Modeling and Characterization 2012, Nov. 2012.
  53. Takanori Moriyasu and Satoshi Ohtake, "A method of LFSR seed generation for scan-based BIST using constrained ATPG," in Proceedings of 2013 Seventh International Conference on Complex, Intelligent, and Software Intensive Systems (5th International Workshop on Virtual Environment and Network-Oriented Applications), pp.755-759, July 2013.
  54. Taro Honda and Satoshi Ohtake, "A method of LFSR seed generation for delay fault BIST using constrained ATPG," 15th IEEE Workshop on RTL and High Level Testing (WRTLT'14), pp.20-25, Nov. 2014.
  55. Shuichi Sato and Satoshi Ohtake, "A delay measurement mechanism for asynchronous circuits of bundled-data model," 15th IEEE Workshop on RTL and High Level Testing (WRTLT'14), pp.84-89,Nov. 2014.
  56. Takanori Moriyasu and Satoshi Ohtake, "A method of one-pass seed generation for LFSR-based deterministic/pseudo-random testing of static faults," in Proceedings of Latin American Test Symposium, March 2015.
  57. Syuichi Sato and Satoshi Ohtake, "A delay measurement mechanism for asynchronous circuits of bundled-data model," in Proceedings of IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2015, pp.243-248, April 2015.
  58. Renji Ono and Satoshi Ohtake, "A method of diagnostic test generation for transition faults," in Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing 2015, pp.273-278, Nov. 2015.
  59. Sho Kano and Satoshi Ohtake, "A field test architecture for circuits configured on FPGAs", 16th IEEE Workshop on RTL and High Level Testing (WRTLT'15), Nov. 2015.
  60. Kosuke Sawaki and Satoshi Ohtake, "A method of LFSR seed generation for hierarchical BIST," in Proceedings of 10th IEEE International Design and Test Symposium, pp.118-123, Dec. 2015.
  61. Daichi Shimazu and Satoshi Ohtake, "An approach to LFSR-based X-masking for built-in self-test," in Proceedings of 18th IEEE Latin American Test Symposium, March 2017.
  62. Yui Uehara, Satoshi Ohtake and Takamoto Fukura, "A mash temperature monitoring system for sake brewing," in Proceedings of IEEE International Conference on Consumer Electronics - Taiwan, May 2018. (To appear)
  63. Yushiro Hiramoto and Satoshi Ohtake, "A method of hardware-Trojan detection using design verification techniques," in Proceedings of 12th International Conference on Complex, Intelligent, and Software Intensive Systems (10th International Workshop on Virtual Environment and Network-Oriented Applications), July 2018.
  64. Yui Uehara and Satoshi Ohtake, "Factory environment monitoring: a Japanese tea manufacturer’s case," in Proceedings of 37th International Conference on Consumer Electronics, Jan. 2019. (To appear) 

Technical Reports

  1. Satoshi Ohtake and Hideo Fujiwara, "Test generation time reduction for sequential circuits by extracting circuit structure," Proceedings of the IEICE General Conference 1996, Vol.1996ISS, No.1, pp. 323-324, Mar. 1996. (In Japanese)
  2. Satoshi Ohtake, Tomoo Inoue and Hideo Fujiwara, "An approach to sequential test generation by circuit pseudo-transformation," Technical Report of IEICE (FTS96-42), Vol. 96, No. 291, Oct. 1996. (In Japanese)
  3. Satoshi Ohtake, Toshimitsu Masuzawa and Hideo Fujiwara, "A non-scan DFT method for controllers to provide complete fault efficiency," Technical Report of IEICE (FTS97-63), Vol.97, No.419, Dec. 1997. (In Japanese)
  4. Debesh K. Das, Satoshi Ohtake and Hideo Fujiwara, "New DFT techniques of non-scan sequential circuits with complete fault efficiency," Technical Report of IEICE (FTS98-115), Vol.98, No.488, pp.73-80, Dec. 1998.
  5. Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa and Hideo Fujiwara, "A Non-scan DFT method at register-transfer level to achieve complete fault efficiency," Technical Report of IEICE (VLD99-81, ICD99-210, FTS99-59), Vol.99, No.479, pp.47-54, Nov. 1999. (In Japanese)
  6. Shintaro Nagai, Hiroki Wada, Satoshi Ohtake and Hideo Fujiwara, "A non-scan DFT method for RTL circuits based on fixed-control testability," Technical Report of IEICE (VLD99-101), pp.29-36, Jan. 2000. (In Japanese)
  7. Md. Altaf-Ul-Amin, Satoshi Ohtake and Hideo Fujiwara, "Analyzing path delay fault testability of RTL data paths: a non-scan approach," Technical Report of IEICE (FTS2000-71, VLD2000-106, ICD2000-163), Vol. 100, No. 473, pp.221-226, Nov. 2000.
  8. Shunjiro Miwa, Satoshi Ohtake,  and Hideo Fujiwara, "A new class of sequential circuits with combinational test generation complexity for path delay faults," Technical Report of IEICE (FTS2000-87), Vol. 100, No. 620, pp.9-16, Feb. 2001. (In Japanese)
  9. Shintaro Nagai, Satoshi Ohtake and Hideo Fujiwara, "A Design for hierarchical testability for RTL data paths using extended data flow graph," Technical Report of IEICE (VLD2001-106, ICD2001-151, FTS2001-53), Vol. 101, No. 467, pp.103-108, Nov. 2001. (In Japanese)
  10. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "A method of partially enhanced scan design for path delay faults based on discontinuous reconvergence structure," Technical Report of IEICE  (FTS2001-84), Vol. 101, No. 658, pp.53-60, Feb. 2002. (In Japanese)
  11. Md. Altaf-Ul-Amin, Satoshi Ohtake and Hideo Fujiwara, "Design for two-pattern testability of controller-data path circuits," Technical Report of IEICE (FTS2001-85), Vol. 101, No. 658, pp.61-67, Feb. 2002.
  12. Kouhei Ohtahi, Satoshi Ohtake and Hideo Fujiwara, "A method of test generation for path delay faults using stuck-at fault test generation algorithms," Technical Report of IEICE (FTS2001-86), Vol. 101, No. 658, pp.69-75, Feb. 2002. (In Japanese)
  13. Shintaro Nagai, Satoshi Ohtake and Hideo Fujiwara, "A DFT method for RTL data paths based on strong testability to reduce test application time," Technical Report of IEICE (DC2002-84), Vol. 102, No. 658, pp.31-36, Feb. 2003. (In Japanese)
  14. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "A method of design for delay fault testability of controllers," Technical Report of IEICE (DC2003-38), Vol. 103, No. 476, pp.25-30, Nov. 2003.
  15. Yuu Murata, Satoshi Ohtake and Hideo Fujiwara, "A method of DFT for data paths using bit-match function," Technical Report of IEICE (DC2004-58), Vol. 104, No. 478, pp.67-72, Dec. 2004. (In Japanese)
  16. Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara, "Design for testability based on single-port-change delay fault testing for data paths," Technical Report of IEICE (DC2004-58), Vol. 104, No. 478, pp.73-78, Dec. 2004. (In Japanese)
  17. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "Equivalence of sequential transition test generation and constrained combinational stuck-at test generation," Technical Report of IEICE (DC2004-96), Vol. 104, No. 664, pp.27-32, Feb. 2005.
  18. Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake and Hideo Fujiwara, "Design for partially strong testability of data paths to guarantee complete fault efficiency," Technical Report of IEICE (DC2004-92), Vol. 104, No. 664, pp.1-6, Feb. 2005. (In Japanese)
  19. Masato Nakazato, Satoshi Ohtake and Hideo Fujiwara, "Acceleration of test generation for sequential circuit using knowledge obtained from synthesis for testability," Technical Report of IEICE (DC2004-97), Vol. 104, No. 664, pp.33-38, Feb. 2005. (In Japanese)
  20. Kousuke Yabuki, Satoshi Ohtake and Hideo Fujiwara, "Delay testing for application-specific interconnects of FPGAs based on inphase structure," Technical Report of IEICE, Vol. 105, No. 442, pp.1-6, Dec. 2005. (In Japanese)
  21. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "A broadside test generation method for transition faults in partial scan circuits," IEICE Technical Report (DC2005-54), Vol. 105, No. 443, pp.7-12, Dec. 2005.
  22. Nobuhiro Yamagata, Masato Nakazato, Kazuko Kambe, Tomokazu Yoneda, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara, "DFT of instruction-based self-test for non-pipelined," Technical Report of IEICE (DC2005-73), Vol. 105, No. 607, pp.7-12, Feb. 2006. (In Japanese)
  23. Masato Nakazato, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara, "Design for testability of software-based self-test for processors," Technical Report of IEICE (ICD2006-48), Vol. 106, No. 92, pp.49-54, June 2006. (In Japanese)
  24. Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko and Hideo Fujiwara, "A test generation framework using checker circuits and its application to path delay test generation," Technical Report of IEICE (CAS2006-76), Vol. 106, No. 512, pp.37-42, Jan. 2007.
  25. Yuki Yoshikawa, Satoshi Ohtake and Hideo Fujiwara, "Reduction in over-testing of delay faults through false paths identification using RTL information," Technical Report of IEICE (DC2006-87), Vol. 106, No. 528, pp.43-48, Feb. 2007.
  26. Naotsugu Ikeda, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara, " RTL false path identification using high level synthesis information," Technical Report of IEICE (DC2007-77), Vol. 107, No. 482, pp.63-68, Feb. 2008. (In Japanese)
  27. Hiroshi Iwata, Satoshi Ohtake and Hideo Fujiwara, "An approach to RTL-GL path mapping based on functional equivalence," Technical Report of IEICE (VLD2008-34), Vol. 108, No. 107, pp.13-18, June 2008. (In Japanese)
  28. Yuichi Uemoto, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara, "Resource Binding to Minimize the Number of RTL paths," Technical Report of IEICE(DC2008-77), Vol.108, No.431, pp.55-60, Feb. 2009. (In Japanese)
  29. Tomokazu Yoneda, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara, "An approach to temperature control during VLSI test," Proceedings of the IEICE General Conference, Vol. D-10-18, pp.161, Mar. 2009.
  30. Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara, "A full scan design method for asynchronous sequential circuits based on C-element scan paths," Technical Report of IEICE (DC2010-8), Vol.110, No.106, pp.1-6, June 2010.
  31. Eri Murata, Satoshi Ohtake and Yasuhiko Nakashima, "A method of thermal uniformity control during BIST," Technical Report of IEICE (DC2011-62), Vol.111, No.325, pp.197-202, Nov. 2011. (In Japanese)
  32. Koki Uchida, Eri Murata, Satoshi Ohtake and Yasuhiko Nakashima, "A test generation method for synchronously designed QDI circuits," Technical Report of IEICE (DC2011-83), Vol.111, No.435, Feb. 2012. (In Japanese)
  33. Takanori Moriyasu amd Satoshi Ohtake, "A method of deterministic LFSR seed generation for scan-based BIST," Technical Report of IEICE (DC2013-11), vol.113, no.104, pp.7-12, June 2013. (In Japanese)
  34. Taro Honda and Satoshi Ohtake, "A method of LFSR seed generation for delay fault BIST," Technical Report of IEICE (DC2013-58), Vol.113, No.321, pp.227-231, Nov. 2013. (In Japanese)
  35. Hiroyuki Nakashima and Satoshi Ohtake, "A method of high quality transition test generation using RTL information," Technical Report of IEICE (DC2013-60), Vol.113, No.321, pp.239-244, Nov. 2013. (In Japanese)
  36. Syuichi Sato and Satoshi Ohtake, "A delay measurement mechanism for asynchronous circuits of bundled-data," IPSJ SIG Technical Report (Hinokuni Joho Symposium 2014), 1A-2, pp.1-8, Mar. 2014. (In Japanese)
  37. Renji Ono and Satoshi Ohtake, "A method of diagnostic test generation for transition faults," IPSJ SIG Technical Report (Hinokuni Joho Symposium 2014), 4A-4, pp.1-6, Mar. 2014. (In Japanese)
  38. Shogo Tetsukawa, Seiya Miyamoto, Satoshi Ohtake, Yoshiyuki Nakamura, "A method of burn-in fail prediction for LSIs based on supervised learning using cluster analysis," Technical Report of IEICE (DC2014-64), Vol.114 , No.329, pp.251-256, Nov. 2014. (In Japanese)
  39. Kosuke Sawaki and Satoshi Ohtake, "A method of LFSR seed generation for hierarchical BIST," Technical Report of IEICE (DC2014-85), Vol.114, No.446, pp.43-48, Feb. 2015. (In Japanese)
  40. Daichi Shimazu and Satoshi Ohtake, "An approach to LFSR/MISR seed generation for delay fault BIST," Technical Report of IEICE (DC2015-66), Vol.115, No.339, pp.213-218, Dec. 2015. (In Japanese)
  41. Hiroki, Ueda, Daichi Shimazu and Satoshi Ohtake, "Design of BIST with soft error resilience for testing FPGAs," Technical Report of IEICE (DC2015-67), Vol.115, No.339, pp.219-224, Dec. 2015. (In Japanese)
  42. Hayato Minamizono and Satoshi Ohtake, "A method of LFSR seed generation for on-chip fault diagnosis," Technical Report of IEICE (DC2016-58), Vol.116, No.331, pp.117-122, Nov, 2016. (In Japanese)
  43. Daichi Yuruki, Satoshi Ohtake and Yoshiyuki Nakamura, "An approach to performance improvement of machine learning based fail chip discrimination," Technical Report of IEICE(DC2016-77), Vol.116, No.466, pp. 17-22, Feb. 2017. (In Japanese)
  44. Keisuke Kagawa, Fumiya Yano, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi and Satoshi Ohtake, "Built-In Self Diagnosis Architecture for Logic Design," Technical Report of IEICE(DC2016-76), Vol.116, No.466, pp. 11-16, Feb. 2017. (In Japanese)
  45. Kyonosuke Watanabe and Satoshi Ohtake, "A method of LFSR seed generation for improvement of delay fault BIST," Technical Report of IEICE(DC2017-41), Vol.117, No.274, pp. 49-54, Nov. 2017. (In Japanese)
  46. Daichi Yuruki, Satoshi Ohtake and Yoshiyuki Nakamura, "An approach to selection of classifiers and their thresholds for machine learning based fail chip prediction," Technical Report of IEICE(DC2017-42), Vol.117, No.274, pp. 55-60, Nov. 2017. (In Japanese)

Invited Papers

  1. Michiko Inoue, Satoshi Ohtake and Hideo Fujiwara, "Partial Scan Designs Equivalent to Full Scan Designs," Proceedings of the IEICE General Conference 2002 (SD-2-10), Vol.2002ISS, No.1, Mar. 2002. (In Japanese)
  2. Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara, "High level design for testability," Proceedings of the IEICE General Conference 2002 (SD-2-11), Vol.2002ISS, No.1, Mar. 2002. (In Japanese)
  3. Yasuo Sato, Seiji Kajihara, Michiko Inoue, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara and Yukiya Miura "Circuit failure prediction by field test (DART) with delay-shift measurement mechanism," Technical Report of IEICE (ICD2010), pp.5-10, Aug. 2010.

Invited Seminars / Talks

  1. Satoshi Ohtake, "A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description," Chulalongkorn University, Bangkok, Thailand, Jan. 2002.
  2. Satoshi Ohtake, "Non-Scan DFT Method at Register-Transfer Level to Achieve Complete Fault Efficiency," Chulalongkorn University, Bangkok, Thailand, Jan. 2002.
  3. Satoshi Ohtake, "Partial Scan Designs for Delay Testing," Jadavpur University, Kolkata, India, Dec. 2005.
  4. Satoshi Ohtake and Tomoo Inoue, "Register Transfer Level Design for Testability," 27th STARC Seminar, Semiconductor Technology Academic Research Center (STARC), Dec. 2007. (In Japanese)
  5. Satoshi Ohtake, "False Path Identification Using RTL Design Information," University of Wisconsin - Madison, Mar. 2009.
  6. Satoshi Ohtake, "Recent techniques of asynchronous circuit testing," 61st FTC Workshop, Odaicho, Mie, July 2009. (In Japanese)

Patents

  1. Title: Testable integrated circuit, integrated circuit design-for-testability method, and computer-readable medium storing a program for implementing the design-for-testability method,
          Inventers: Hideo Fujiwara, Toshimitsu Masuzawa and Satoshi Ohtake,
          Patent No.: Japan: No.3243207 (Oct. 19, 2001), USA: No.6334200B1, Taiwan: No.111808, EPC: No.98121985.0.
  2. Title: Integrated circuit with design for testability and method for designing the same,
          Inventers: Hideo Fujiwara, Toshimitsu Masuzawa and Satoshi Ohtake,
          Patent No.: Japan: No.3349123 (Sep. 13, 2002), USA: No.09/699478, Korea: No.2000-64278, Taiwan: No.89122752, Germany: No.1005272.3.
  3. Title: Scannable C-element and semiconductor integrated circuit containing the scannable C-element and methods for design and test pattern generation of the circuit,
          Inventors: Satoshi Ohtake, Hiroshi Iwata and Michiko Inoue,
          Application No.: Japan: Application No. 2010-138609 (June 17, 2010).
  4. Title: Scannable asynchronous memory elements and semiconductor integrated circuit containing the scannable asynchronous memory elements and methods for design and test pattern generation of the circuit,
          Inventors: Satoshi Ohtake, Hiroshi Iwata and Michiko Inoue,
          Application No.: PCT JP2011-03405 (June 15, 2011), Taiwan 100121280 (June 17, 2011).
  5. Title: Asynchronous memory element for scanning,
          Inventors: Satoshi Ohtake, Hiroshi Iwata and Michiko Inoue,
          Application No.: USA 13/715,929 (Dec. 14, 2012) 
  6. Title: A method of LFSR seed generation of scan-based BIST
          Inventors: Satoshi Ohtake and Takanori Moriyasu,
          Application No.: Japan 2013-148812 (July 17, 2013)
  7. Title: A method of LFSR seed generation of scan-based BIST for delay faults
          Inventors: Satoshi Ohtake and Taro Honda,
          Application No.: Japan 2013-148663 (July 17, 2013)
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